1. Field
This disclosure relates generally to data processing systems, and more specifically, to cache and memory coherency of information in data processing systems.
2. Related Art
Data processing systems typically use multiple processors, each having a closely coupled cache memory, coupled via a system communication bus to a system memory. Cache memory stores a subset of duplicative information that is stored in the system memory. Each cache in the system reduces the number of occurrences that a processor must communicate with the system memory via the system communication bus.
To maintain cache and memory coherency, reads and writes of shared information to the system memory are monitored or “snooped”. When either a memory read or a memory write of data at an address which is shared by more than one master or cache in the system is detected, this address is used as a snoop address. A snoop request is initiated and directed to one or more cache memories in the system to search for any address in the caches that match the snoop address. A snoop hit occurs for every match, and any needed corrective action is taken to maintain coherency of the data corresponding to the address in the cache where the snoop hit occurs. In one form each cache memory has a snoop storage buffer or queue for storing received snoop requests. When a large number of bus transactions occur, the snoop storage buffer may readily become full. When the queue resources are not available due to the snoop queue being filled to capacity, a flow control mechanism is used to prevent snoop activity from being lost or overrunning the snoop queue. Some existing systems delay responding to a current transaction until resources are available. However, the delay stalls the system bus and blocks bus activity from occurring until the snoop transactions are processed.